Integrated circuits produced by SOI technology exhibit a certain number of advantages. Such circuits generally exhibit lower electrical consumption for equivalent performance. Such circuits generally induce lower parasitical capacitances, which make it possible to improve the switching speed. Moreover, the phenomenon of parasitic triggering (“latch-up”) encountered by MOS transistors in Bulk technology can be avoided. Such circuits therefore turn out to be particularly suitable for applications of SoC or MEMS type. It is also noted that SOI integrated circuits are less sensitive to the effects of ionizing radiations and therefore turn out to be more reliable in applications where such radiations may induce operational problems, in particular in space applications. SOI integrated circuits can in particular comprise random-access memories of SRAM type or logic gates.
In a known manner, such integrated circuits also include devices for protecting against accidental electrostatic discharges (ESD) that can impair these transistors.
The design of an ESD device is produced to observe certain technological restrictions. FIG. 1 is an example of a current-voltage diagram of an ESD device during a discharge. Upon the appearance of an electrostatic discharge, the voltage across the terminals of the ESD device first increases to a trigger voltage Vt1. The current passing through the ESD device therefore increases slightly (low leakage). This voltage Vt1 must remain below a voltage Vm, corresponding to a breakdown voltage in MOS technology, typically of 2.6 V for FDSOI with a technological node of 28 nm. The voltage Vt1 is also greater than a supply voltage Vdd of the various circuits in order to avoid accidental triggering of the ESD device. The voltage Vt1 is thus typically above a voltage of 1.1*Vdd.
When the triggering voltage Vt1 is reached, the ESD device is triggered. Firstly, the voltage across the terminals of the ESD device can decrease, the current passing through it continuing to rise. Secondly, the voltage across the terminals of the ESD device increases, in the same way as the current passing through it in order to short-circuit the electrostatic discharge current. In this second step, the ESD device must exhibit as low an on-resistance as possible, in order to exhibit as high a maximum short-circuit current It2 as possible for a voltage below the voltage Vm.
Moreover, the ESD device must generally have as low a leakage current as possible before being triggered in order to reduce the electricity consumption of the integrated circuit.
ESD devices often occupy a non-negligible surface region of the integrated circuit, which it is desirable to minimize. Moreover, the fabrication process of an ESD device must entail a minimum of additional steps to avoid excessively increasing the cost of the integrated circuit.
The document US20050212051 describes an ESD device comprising a pnp bipolar transistor and an npn bipolar transistor, formed on a thick layer of buried insulant. Base contacts are formed by heavily doped side regions. An additional circuit provides control of discharge currents on base contacts.
This ESD device does exhibit several drawbacks, however. An additional circuit is required to ensure the control of discharge current by way of the MOS transistor, which entails a drop in integration density and increased complexity of the integrated circuit. Such an ESD device furthermore exhibits a great complexity of interconnection, and requires the optimization of the doping of the bases, which therefore entails the use of a large number of photolithographic masks.
The document U.S. Pat. No. 7,791,102 describes an ESD device comprising a pnp bipolar transistor and an npn bipolar transistor, formed on a thick buried insulant layer. The base of the pnp transistor is connected to the collector of the npn transistor. The collector of the pnp transistor is connected to the base of the npn transistor. A MOS transistor is formed on the npn transistor and connected between the collector and the emitter of this transistor. The MOS transistor makes it possible to limit the maximum voltage across the terminals of the ESD device, makes it possible to control the amplitude of the discharge current and makes it possible to limit the leakage current.
This ESD device does however exhibit several drawbacks. An additional circuit is necessary to ensure the control of the discharge current by way of the MOS transistor, which entails a drop in integration density and increased complexity of the integrated circuit. Moreover, this circuit exhibits deteriorated reliability, linked to the dimensions of the gate oxide of the MOS transistor formed on the npn transistor. The presence of the MOS transistor furthermore entails a reduction in thickness of the npn and pnp transistors, and consequently an increase in the on-resistance during the triggering of the ESD device. Such an ESD device furthermore exhibits a great complexity of interconnection, and requires the optimization of the doping of the bases, which therefore entails the use of a large number of photolithographic masks.
There is a need for an integrated circuit including a device for protecting against electrostatic discharges solving one or more of these drawbacks.